The present invention relates to a phase lock loop (PLL) for carrier regeneration, and/or clock regeneration in radio communication and satellite communication systems.
In digital radio communication and satellite communication systems using PSK (Phase Shift Keying) modulation, a receiver demodulates a PSK signal through a coherent detection which has excellent demodulation characteristics for transmission errors. In the coherent detection, a demodulator must have an accurate carrier which synchronizes with the phase of the transmitted carrier, and also has the same frequency as that of the transmitted carrier. To regenerate the carrier in the receiver, a PLL or a tuning circuit has been used.
In a mobile communication system, and/or a satellite communication system, there is a high channel noise, a large frequency offset, and a frequency shift caused by a doppler effect in the carrier frequency. These factors degrade the performance of the carrier recovery, and it is sometimes difficult to regenerate a stable carrier, resulting in a synchronization loss in such systems. Also, the PLL takes a long time to complete the pull-in and lock-in stages, and also the PLL falls out of lock often even after the PLL locked in.
To solve the above problems, it has been proposed to use a preamble long enough for the carrier regeneration. However, the transmission efficiency decreases. Further, if the synchronization loss in the system happens once because of the channel noise, fading disturbances, or the frequency shift after the synchronization is established, no carrier regeneration is possible in the receiving side, since no preamble is obtained.
In a low rate radio packet transmission system, no preamble is attached to a packet in view of transmission efficiency. In this system, the PLL which acquire the lock-in quickly and stably, and hold it tightly under a low C/N (Carrier to Noise power ratio) condition having a high noise has not been found.
FIG. 1 shows a block diagram of a prior carrier regeneration system which uses a digital PLL. A PSK modulation signal is applied to an input terminal (1) and is processed by a frequency multiplier (2) to generate a carrier component which is an integer multiple of a carrier frequency. The frequency multiplier (2) denotes a frequency doubler in case of two phase modulation, and a tripler in case of four phase modulation. The output of the frequency multiplier (2) is then applied to the conventional PLL (5) through the bandpass filter (3) from the PLL input terminal (4). The PLL (5) provides a VCO output which is locked-in with the carrier component and is free from the channel noise, and is obtained at the output terminal (6). The frequency divider (7) divides the frequency of the VCO output, and provides the regenerated carrier at the output terminal (8).
It should be appreciated in FIG. 1 that the input signal is supposed to be a digital signal, and all the elements in figures described in this invention operate in digital.
The PLL (5) has a phase detector (10) which detects the phase error between the input signal at the terminal (4) and the reference signal of the VCO output, a loop filter (11) coupled with the output of the phase detector (10), and a digital voltage controlled oscillator of VCO (9) as a reference signal generator. The VCO (9) consists of an accumulator (12), a center frequency generator (13), an initial phase generator (14), a cosine converter (15), and adders (16 and 17). The phase detector (10) receives the reference signal of the VCO output having a cosine waveform with the initial phase .theta..sub.0 and the center frequency W.sub.0, and the input signal having the carrier component from the input terminal (4). The phase difference and/or the frequency difference between the VCO output and the input signal is detected as the phase error by the phase detector (10), and then the output is applied to the loop filter (11) which suppresses undesired noise component. The bandwidth and gain of the PLL loop determines the performance of the pull-in and the lock-in.
The frequency of the VCO (9) is determined by the error signal from the loop filter (11) and the output of the center frequency generator (13) which provides a signal corresponding to the center frequency. The phase of the VCO (9) is also determined by the output of the accumulator (12), and the output of the initial phase generator (14) which provides a signal corresponding to the initial phase. The error signal from the loop filter (11) is added to the output of the center frequency generator (13) through the adder (16), and then is fed to the accumulator (12) which accumulates it at every sampling time. The output of the accumulator (12) is added to the output of the initial phase generator (14) through the adder (17), and then is fed to the cosine converter (15) which generates a cosine waveform as the VCO output. The output of the VCO (9) is applied to the phase detector (10) as a reference signal to the input signal. The locked VCO output is obtained at the output terminal (6), and the output frequency is divided by the frequency divider (7) which provides the regenerated carrier. The VCO (9) operates first to complete the pull-in stage for coinciding the frequency, and next to complete lock-in stage for the phase lock.
Since the circuit elements operate in digital, it should be noted that the center frequency generator (13) and the initial phase generator (14) provide a constant level corresponding to the center frequency and the initial phase, respectively. When the accumulator (12) accumulates the constant level signal corresponding to the center frequency at every sampling time, the output of the accumulator (12) becomes a ramp signal increasing with time. Also the accumulator (12) outputs a constant level signal to compensate the initial phase to the phase of the input signal. The initial phase generator (14) prepares the constant level signal corresponding to the initial phase to determine the initial phase of the VCO. The cosine converter (15) converts the input to the cosine waveform in a digital form. The output of the loop filter eventually adjusts the frequency and the phase of the VCO output through the accumulator (12) instantaneously. Therefore, it should be appreciated that the VCO (9) in FIG. 1 performs just as a conventional analog voltage controlled oscillator.
The frequency multiplier (2) increases the noise level by 6 dB in BPSK, and the phase detector (10) using a multiplier also generates some additional noise caused by the non-linear operation. Noise causes the pull-in and lock-in times longer, and further causes the out of lock after the lock-in state was achieved once. Therefore, when the C/N is very low, a stable carrier regeneration becomes difficult. Particularly, when a frequency offset and/or a frequency shift are large, the above problem becomes more serious.
When the loop gain of the PLL (5) is high, the pull-in and the lock-in times are short, however the sensitivity to noise becomes high, resulting in a large phase jitter and a frequency jitter in the VCO output at the terminal (6). On the other hand, when the loop gain of the PLL (5) is low and the bandwidth of the loop is narrow to remove the noise, the pull-in and lock-in capabilities for the frequency offset and the initial phase difference become low, resulting in narrower pull-in and lock-in ranges. Accordingly, it is difficult for the loop to lock, and a carrier loss happens. For example, when the value of the C/N is lower than 3 dB, it is almost impossible to regenerate the stable carrier in a prior art. Further, the prior phase detector using a multiplier has a disadvantage of a false lock.
The narrow bandwidth of the loop would have the disadvantage of taking a long time to achieve the lock-in state for the large frequency offset, and of being difficult to hold the lock-in state for the frequency shift. Conventionally, some improvements in the performance have been achieved by adjusting the bandwidth and gain of the loop, depending on whether it is before or after the lock-in stage, and/or by using a phase detector having a linear phase detection characteristics. For instance, the bandwidth of the loop is first set wider at the kick-off stage, considering the frequency offset, and then the bandwidth of the loop is switched narrower to avoid the out of lock state due to noise after the pull-in condition is established.
However, the mere switching of the loop gain and/or the bandwidth is insufficient to achieve a stable carrier recovery in an extremely low C/N condition having a large frequency offset in mobile satellite communications.
Further, a prior tuning circuit cannot regenerate the carrier in case of the large frequency offset, and/or the large doppler frequency shift.